Analysis tool

DynaCore - A timing sign-off solution for custom block and full chip static-timing analysis for SoC, with SPICE accuracy and built-in optimum vector generation.
DynaCore is a next-generation, timing analysis, and modeling tool for multi-million-transistor designs. Designers have the capability to time the entire design at the SPICE level, using either Circuit Semantics' built-in SPICE engine or an external commercial simulator, and then running Circuit Semantics' STA. The DynaCore STA environment allows both custom and ASIC design flows to co-exist. DynaCore enables designers to quickly analyze timing bottlenecks, produce critical and sub-critical paths, slack analysis, and various types of timing models. In addition, Cadence's Pearl and Synopsys' PrimeTime are supported. Another key capability is incremental characterization, resulting in vastly decreased times for ECO's.

DynaModel - An automated Verilog Model generation of custom designs for functional validation.

DynaModel extracts a Verilog gate-level simulation model from custom designs including hard IP. All logic in the initial transistor-level design is precisely represented in the resulting Verilog model. It handles both static and dynamic design styles. DynaModel significantly accelerates functional simulation. It models a transistor-level design at a higher level of abstraction for use in verification flows signoff.